The present invention generally relates to integrated circuits, and more particularly, to a voltage regulator.
Integrated circuits (ICs) such as systems-on-chips (SoCs) and application specific integrated circuits (ASICs) integrate various analog and digital components on a single chip. These components require stable supply voltage signals for performing operations. Thus, ICs include voltage regulators for regulating supply voltage signals. A voltage regulator rejects noise injected into a supply voltage signal (measured as Power Supply Rejection Ratio (PSRR)) from a voltage source and provides a regulated output signal to IC components. For example, a linear regulator with a high PSRR (>20 dB) is needed for low jitter Gigabit signals.
Referring now to FIG. 1, a schematic block diagram of a conventional voltage regulator 100 is shown. The voltage regulator 100 includes an error amplifier 102, a transistor 104, a compensation capacitor 106, and a resistive network 108. The voltage regulator 100 is connected to a load capacitor 110 and a load impedance 112.
The error amplifier 102 has a first input terminal for receiving a reference signal (VREF) and a second input terminal for receiving a feedback signal (VFB). The reference signal is a bandgap reference voltage signal. The error amplifier 102 amplifies a difference between the voltage levels of the two input signals and generates a control signal VCONT.
The transistor 104 has a source terminal for receiving a supply voltage signal (VDD), a gate terminal that receives the control signal VCONT, and a drain terminal for generating an output signal (VOUT).
The compensation capacitor 106 has a first terminal connected to the gate terminal of the transistor 104, and a second terminal connected to the drain terminal of the transistor 104. The compensation capacitor 106 increases stability of the voltage regulator 100 by splitting poles of the voltage regulator 100. Thus, the stability of the voltage regulator 100 is increased by a technique known as “pole-splitting” (also known as “Miller compensation”).
The resistive network 108 is a voltage divider and includes first and second resistors 114 and 116 connected in series between the drain terminal of the transistor 104 and ground. The resistive network 108 also has a voltage tap for outputting the feedback signal VFB.
The load capacitor 110 has a first terminal connected to the drain terminal of the transistor 104 for receiving the output signal and a second terminal connected to ground. The load capacitor 110 increases the stability of the voltage regulator 100. The load capacitor 110 and the load impedance 112 form the load of the voltage regulator 100.
Ripples (noise) in the supply voltage signal cause the voltage level of the output signal to deviate from a desired voltage level, which results in the deviation of the voltage level of the feedback signal from a desired voltage level, i.e, the voltage level of the reference signal. When the voltage level of the feedback signal is less than the voltage level of the reference signal, the error amplifier 102 amplifies the difference between the voltage levels of the feedback signal and the reference signal and generates the control signal, and the current through the transistor 104 increases, which restores the voltage level of the output signal to the desired voltage level. When the voltage level of the feedback signal is greater than the voltage level of the reference signal, the error amplifier 102 amplifies this difference and generates the control signal where the current through the transistor 104 decreases, which restores the voltage level of the output signal to the desired voltage level. Thus, the voltage regulator 100 provides a regulated output signal.
The voltage regulator 100 works efficiently for ripples frequencies less than about 100 megahertz (MHz), but fails to maintain a PSRR about 20 decibels (dB), for ripple frequencies between 100 MHz and 1000 MHz because the bandwidth of the error amplifier 102 is impacted negatively by a pole formed at 100 MHz due to capacitances at the output of the error amplifier 102. The capacitances at the output of the error amplifier 102 include a capacitance of the gate of the transistor 104 and a Miller effect capacitance of the compensation capacitor 106. The PSRR of the voltage regulator 100 is a measure of effectiveness of the voltage regulator 100 in rejecting noise in the supply voltage signal. However, the PSRR of the voltage regulator 100 improves at ripple frequencies greater than 1000 MHz because the load capacitor 110 provides a low impedance to ground. Thus, the voltage regulator 100 fails to maintain the absolute value of the PSRR above the desired level for ripples frequencies between 100 and 1000 MHz. Further, the size of the transistor 104 is large for driving heavy loads, which increases the area of a device that includes the voltage regulator 100.
Techniques to overcome the aforementioned problems involve complex circuits that tend to increase the overall circuit area and power consumption.
Therefore, it would be advantageous to have a voltage regulator that provides a regulated output signal at all frequencies without unnecessarily increasing circuit are and power consumption.